資源簡介
32位超前進位快速加法器
經過Isim仿真測試正確的32位超前加法器
編寫語言Verilog-HDL
基于zhaohongliang代碼
修改了其中部分有問題的模塊
代碼片段和文件信息
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????文件???????1241??2011-11-02?17:16??testbench\adder_test.v
?????文件???????3023??2011-10-26?15:28??頂層\adder_top.v
?????文件????????867??2011-10-26?15:05??三個底層模塊\adder_cell.v
?????文件????????801??2011-10-26?15:17??三個底層模塊\adder_inc.v
?????文件????????650??2011-10-26?13:18??三個底層模塊\adder_logic.v
?????目錄??????????0??2011-11-02?17:16??testbench
?????目錄??????????0??2011-11-02?17:16??頂層
?????目錄??????????0??2011-11-02?17:19??三個底層模塊
-----------?---------??----------?-----??----
?????????????????6582????????????????????8
-----------?---------??----------?-----??----
?????文件???????1241??2011-11-02?17:16??testbench\adder_test.v
?????文件???????3023??2011-10-26?15:28??頂層\adder_top.v
?????文件????????867??2011-10-26?15:05??三個底層模塊\adder_cell.v
?????文件????????801??2011-10-26?15:17??三個底層模塊\adder_inc.v
?????文件????????650??2011-10-26?13:18??三個底層模塊\adder_logic.v
?????目錄??????????0??2011-11-02?17:16??testbench
?????目錄??????????0??2011-11-02?17:16??頂層
?????目錄??????????0??2011-11-02?17:19??三個底層模塊
-----------?---------??----------?-----??----
?????????????????6582????????????????????8
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