資源簡介
無線通信fpga設計(田耘),上面詳細的介紹了fpga在無線通信方面的開發流程,我當初可是費了很大的功夫找到的哦!
代碼片段和文件信息
fs?=?12e6;?%采樣頻率
ts?=?1/fs;?
num?=?2.5e6;??%數據長度
SNR?=?-15;
real_fc?=?3563000;?%實信號頻率
data?=?sin(2*pi*real_fc*(0:num-1)*ts+pi/4)+sqrt(10^(SNR/10))*randn(1num);?%科斯塔斯環的輸入信號
fc?=?3562800;?%本地頻率
?
n?=?fs/1000;?%累積時間為1ms
nn?=?[0:n-1];
nf?=?floor(length(data)/n);%?將輸入數據分成1ms的多個數據塊
wfc?=?2*pi*fc;??%本地信號
phi_prv?=?0;
temp?=?0;
frame?=?0;
carrier_phase?=?0;
phase?=?0;
?
%環路濾波器的參數
c1?=?153.7130;
c2?=?6.1498;
for?frame=1:nf?
%?產生本地的sin和cos函數
expcol?=?exp(j*(wfc*ts*nn+phase));
sine?=?imag(expcol);???
cosine?=?real(expcol);
x?=?data((1:n)+((frame-1)*n));
%將數據轉換到基帶
x_sine?=?x.*sine;
x_cosine?=?x.*cosine;
?
Q?=?sum(x_sine);??????%經過濾波器
I?=?sum(x_cosine);
phase_discri(frame)?=?atan(Q/I);???%得到鎖相環的輸入
?
%鎖相環
dfrq?=?c1*phase_discri(frame)+temp;?%經過環路濾波器
temp?=?temp+
?屬性????????????大小?????日期????時間???名稱
-----------?---------??----------?-----??----
?????目錄???????????0??2007-10-09?01:49??Verilog代碼\
?????目錄???????????0??2007-10-09?01:02??Verilog代碼\c10\
?????目錄???????????0??2007-10-09?00:56??Verilog代碼\c10\10-2\
?????文件????????1254??2007-08-06?20:49??Verilog代碼\c10\10-2\mult.xco
?????文件????????1236??2007-08-06?21:06??Verilog代碼\c10\10-2\mydds.xco
?????文件????????1871??2007-08-07?09:47??Verilog代碼\c10\10-2\square_syn.v
?????目錄???????????0??2007-10-09?00:59??Verilog代碼\c10\10-4\
?????文件?????????800??2007-08-09?11:26??Verilog代碼\c10\10-4\coastas_dds.v
?????文件?????????830??2007-10-07?14:40??Verilog代碼\c10\10-4\costas_lf.v
?????文件????????1589??2007-08-09?11:36??Verilog代碼\c10\10-4\costas_loop.v
?????文件?????????780??2007-08-09?11:31??Verilog代碼\c10\10-4\costas_lpf.v
?????文件????????1146??2007-10-07?14:21??Verilog代碼\c10\10-4\costas_mult.v
?????文件?????????811??2007-08-09?10:53??Verilog代碼\c10\10-4\err_mult.v
?????文件????????1225??2007-08-09?09:49??Verilog代碼\c10\10-4\fir_lpf.xco
?????文件????????1254??2007-08-06?20:49??Verilog代碼\c10\10-4\mult.xco
?????文件????????1246??2007-08-09?11:10??Verilog代碼\c10\10-4\my_dds.xco
?????目錄???????????0??2007-10-09?01:01??Verilog代碼\c10\10-6\
?????文件????????1132??2007-09-25?19:46??Verilog代碼\c10\10-6\dearly_sub.v
?????文件????????1632??2007-09-25?19:19??Verilog代碼\c10\10-6\dedds.v
?????文件????????1396??2007-09-26?01:21??Verilog代碼\c10\10-6\delay_early_gate.v
?????文件????????1247??2007-09-25?10:58??Verilog代碼\c10\10-6\de_mult.xco
?????文件????????1240??2007-09-25?15:12??Verilog代碼\c10\10-6\eddds.xco
?????文件????????1149??2007-09-25?14:46??Verilog代碼\c10\10-6\iir.v
?????文件????????1128??2007-09-25?15:00??Verilog代碼\c10\10-6\iir1.v
?????目錄???????????0??2007-10-09?01:03??Verilog代碼\c10\10-8\
?????文件????????1979??2007-09-29?14:07??Verilog代碼\c10\10-8\baker.v
?????目錄???????????0??2007-10-09?01:16??Verilog代碼\c11\
?????目錄???????????0??2007-10-09?01:14??Verilog代碼\c11\11-10\
?????文件????????1023??2007-09-12?15:55??Verilog代碼\c11\11-10\div16.xco
?????文件????????4682??2007-10-02?00:23??Verilog代碼\c11\11-10\fir_rls.v
?????文件????????1247??2007-09-30?00:58??Verilog代碼\c11\11-10\rlsmult.xco
............此處省略271個文件信息
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