FPGA上運(yùn)行人臉識(shí)別源代碼，This project attempts to realize a face detector using Voila-Jones algorithm. The reference C model is borrowed from [5kk73 GPU Assignment 2012](https://sites.google.com/site/5kk73gpu2012/assignment/viola-jones-face-detection), with some modify to fit hardware implementation and fixed some bug. The code is written by Verilog/SystemVerilog and Synthesized on Xilinx KintexUltrascale FPGA using Vivado. This code is just experimental for function, a lot of optimization can further be done.