資源簡(jiǎn)介
用verilog實(shí)現(xiàn)的mips流水線處理器源代碼，包括數(shù)據(jù)存儲(chǔ)器、指令存儲(chǔ)器、ALU、外設(shè)、控制器、寄存器堆、整個(gè)連接模塊
代碼片段和文件信息
?屬性????????????大小?????日期????時(shí)間???名稱
-----------?---------??----------?-----??----
?????文件???????7237??2012-07-19?16:03??whole1_addb.v
?????文件??????16152??2012-07-20?14:52??whole2_addb.v
?????文件???????7363??2012-07-09?22:59??ALU.v
?????文件???????7836??2012-06-30?11:45??ALU2.v
?????文件???????1953??2012-07-19?15:26??chaoqian.v
?????文件???????7243??2012-07-07?21:31??contrl_forpipe.v
?????文件???????9721??2012-07-06?10:57??contrl2.v
?????文件????????475??2012-07-23?15:31??DataMem.v
?????文件???????1273??2012-07-23?15:31??Peripheral.v
?????文件????????930??2012-07-23?15:30??regfile.v
?????文件??????10194??2012-07-23?15:26??rom.v
?????文件????????547??2012-07-20?16:20??te_whole1.v
-----------?---------??----------?-----??----
????????????????70924????????????????????12
-----------?---------??----------?-----??----
?????文件???????7237??2012-07-19?16:03??whole1_addb.v
?????文件??????16152??2012-07-20?14:52??whole2_addb.v
?????文件???????7363??2012-07-09?22:59??ALU.v
?????文件???????7836??2012-06-30?11:45??ALU2.v
?????文件???????1953??2012-07-19?15:26??chaoqian.v
?????文件???????7243??2012-07-07?21:31??contrl_forpipe.v
?????文件???????9721??2012-07-06?10:57??contrl2.v
?????文件????????475??2012-07-23?15:31??DataMem.v
?????文件???????1273??2012-07-23?15:31??Peripheral.v
?????文件????????930??2012-07-23?15:30??regfile.v
?????文件??????10194??2012-07-23?15:26??rom.v
?????文件????????547??2012-07-20?16:20??te_whole1.v
-----------?---------??----------?-----??----
????????????????70924????????????????????12
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