?屬性????????????大小?????日期????時(shí)間???名稱(chēng)
-----------?---------??----------?-----??----

?????文件?????165042??2014-09-23?18:46??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter15.zip

?????文件?????349318??2014-09-23?18:33??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter16.zip

?????文件?????744853??2014-09-23?18:33??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter17.zip

?????文件?????621719??2014-09-23?18:33??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter18.zip

?????文件????2318332??2014-09-23?18:31??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter01.zip

?????文件?????258667??2014-09-11?21:54??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter02.zip

?????文件?????140757??2014-09-11?21:55??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter04.zip

?????文件????1065485??2014-09-11?21:55??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter05.zip

?????文件?????580258??2014-09-11?21:55??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter06.zip

?????文件???????4386??2014-09-23?18:30??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter07.zip

?????文件?????139481??2014-09-23?18:30??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter08.zip

?????文件?????846207??2014-09-23?18:30??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter09.zip

?????文件??????46777??2014-09-23?18:30??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter10.zip

?????文件?????848817??2014-09-23?18:30??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter12.zip

?????文件?????651893??2014-09-23?18:30??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter13.zip

?????文件?????126770??2014-09-11?21:53??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter14.zip

?????文件????3296192??2014-09-23?18:33??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter19.zip

?????文件?????199580??2014-09-23?18:34??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter20.zip

?????文件???15580431??2014-09-23?18:34??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter21.zip

?????文件???17091319??2014-09-23?18:36??《Verilog?HDL設(shè)計(jì)與實(shí)戰(zhàn)》Chapter22.zip

-----------?---------??----------?-----??----

?????????????45076284????????????????????20